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D a t a S h e e t , R e v . 1 . 1 , M ay . 2 00 4
HYS64D64020[H/G]DL-5-B HYS64D64020[H/G]DL-6-B
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , R e v . 1 . 1 , M ay . 2 00 4
HYS64D64020[H/G]DL-5-B HYS64D64020[H/G]DL-6-B
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS64D64020[H/G]DL-5-B, HYS64D64020[H/G]DL-6-B Revision History: Previous Version: Page 17 7 8 Rev. 1.1 Rev. 1.0 2004-05 2003-03
Subjects (major changes since last revision) Updated IDD values added Black TSOP DDR333 and DDR400 editorial change
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 16 18
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Sheet
5
Rev. 1.0, 2004-05
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM
HYS64D64020[H/G]DL-5-B HYS64D64020[H/G]DL-6-B
1
1.1
* * * * * * * * * * * * *
Overview
Features
Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules Two ranks 64M x 64 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5 V ( 0.2 V) power supply and +2.6 V ( 0.1 V) for DDR400 Built with 512 Mbit DDR SDRAMs organised as x16 in P-TSOPII-66 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM Jedec standard form factor: 67.60 mm x 31.75 mm x 3.80 mm Jedec standard reference layout Raw Cards A DDR400 speed grade supported Gold plated contacts Performance -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz Component Module @CL3 @CL2.5 @CL2
Table 1
Part Number Speed Code Speed Grade max. Clock Frequency
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
The HYS64D64020[H/G]DL-5-B and HYS64D64020[H/G]DL-6-B are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M x64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Overview Table 2 Type Ordering Information Compliance Code Description SDRAM Technology
PC3200 (CL=3.0) HYS64D64020GDL-5-B PC2700 (CL=2.5) HYS64D64020GDL-6-B PC3200 (CL=3.0) HYS64D64020HDL-5-B PC2700 (CL=2.5) HYS64D64020HDL-6-B Notes 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D64020[H/G]DL-5-B, indicating rev. B dies are used for SDRAM components. 2. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "2033-0" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module. PC2700S-2533-0-A1 two ranks 512MB SO-DIMM 512 MB(x16) PC32100S-3033-1-A1 two ranks 512MB SO-DIMM 512 MB (x16) PC2700S-2533-0-A1 two ranks 512MB SO-DIMM 512 MB(x16) PC32100S-3033-1-A1 two ranks 512MB SO-DIMM 512 MB (x16)
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3 Pin# 112 111 110 109 108 107 106 I I I SSTL SSTL SSTL Clock Signal Clock Signal Clock Signal Note: ECC module NC NC I I I - SSTL SSTL SSTL Note: non-ECC module type type 100 99 105 102 101 115 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type I I I I I I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC 123 A13 NC I - SSTL Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit module NC NC - based Address Bus 11:0 Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12
The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Pin Configuration of SO-DIMM Pin Buffer Function Type Type
Name
Clock Signals 35 160 89 CK0 CK1 CK2
37 158 91
CK0 CK1 CK2
Complement Clock Complement Clock Complement Clock Note: ECC module type type
NC 96 95 CKE0 CKE1 NC 121 122 S0 S1 NC 118 120 119 117 116 RAS CAS WE BA0 BA1
NC I I NC I I NC I I I I I
- SSTL SSTL - SSTL SSTL - SSTL SSTL SSTL SSTL SSTL
Note: non-ECC module
Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Data Signals Chip Select Rank 0 Chip Select Rank 1 Note: 2-ranks module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Bank Address Bus 1:0 5 7 13 17 6 8 14 18 19 23 29 31 20 24 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Note: Module based on 512 Mbit or smaller dies Data Bus 63:0
Control Signals
Address Signals
Data Sheet
8
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration Table 3 Pin# 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL NC NC - 74 NC CB5 NC I/O - SSTL 72 CB4 I/O SSTL NC NC - 83 NC CB3 NC I/O - SSTL 79 CB2 I/O SSTL NC NC - 73 NC CB1 NC I/O - SSTL Data Bus 63:0 Table 3 Pin# 172 176 177 181 187 189 178 182 188 190 71 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Check Bit 0 Note: ECC module Note: Non-ECC module Check Bit 1 Note: ECC module Note: Non-ECC module Check Bit 2 Note: ECC module Note: Non-ECC module Check Bit 3 Note: ECC module Note: Non-ECC module Check Bit 4 Note: ECC module Note: Non-ECC module Check Bit 5 Note: ECC module Note: Non-ECC module type type type type type type Data Bus 63:0
Name DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53
Name DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0
Data Sheet
9
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration Table 3 Pin# 80 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type I/O SSTL Check Bit 6 Note: ECC module NC 84 CB7 NC I/O - SSTL Note: Non-ECC module Check Bit 7 Note: ECC module NC 11 25 47 61 133 147 169 183 77 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobe 8 Note: ECC module NC 12 26 48 62 134 148 170 184 78 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 NC I I I I I I I I I - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask 8 Note: ECC module NC EEPROM 195 193 194 196 198 SCL SDA SA0 SA1 SA2 I I/O I I I CMOS Serial Bus Clock OD Serial Bus Data CMOS Slave Address CMOS Select Bus 2:0 CMOS NC - Note: Non-ECC module type Note: Non-ECC module Data Mask 7:0 type Note: Non-ECC module Data Strobes 7:0 Note: See block diagram for corresponding DQ signals type type Table 3 Pin# Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type AI - I/O Reference Voltage EEPROM Power Supply Power Supply
Name CB6
Name
Power Supplies 1,2 197 9,10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192
VREF
VDDSPD PWR - VDD
PWR -
Data Sheet
10
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration Table 3 Pin# 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 199 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type GND - Ground Plane Table 3 Pin# 85, 86, 97, 98, 124, 200 Pin Configuration of SO-DIMM (cont'd) Pin Buffer Function Type Type NC - Not connected Note: Pins connected Infineon DIMMs not on SO
Name
Name NC
VSS
Table 4 I O I/O AI PWR GND NC
Abbreviations for Pin Type Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Abbreviation Description
Table 5 SSTL LV-CMOS
Abbreviations for Buffer Type Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation Description
CMOS
OD
Other Pins
VDDID
O
OD
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB
Data Sheet
11
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration
VREF DQ0 VDD DQ2 DQ3 VDD DQS1 DQ10 VDD CK0 -
Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037
VSS DQ1 DQS0 VSS DQ8 DQ09 VSS DQ11 CK0 VSS -
Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039
Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040
- VSS - DQ6 - DM0 - VSS - DQ12 - DQ13 - VSS - DQ15 - VDD - VSS
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 -
VREF DQ4 VDD DQ6 DQ7 VDD DM1 DQ14 VDD VSS DQ20 VDD DQ22 DQ23 VDD DM3 DQ30 VDD CB5/NC DM8/NC VDD NC VSS VDD NC A8 A6 A2 VDD RAS S1/NC VSS DQ37 DM4 VSS DQ44 DQ45 VSS DQ47 CK1 VSS DQ53 DM6 VSS DQ60 DQ61 VSS DQ63 SA0 SA2 MPPD0040
DQ16 VDD DQ18 DQ19 VDD DQS3 DQ26 VDD CB1/NC DQS8/NC VDD NC CK2/NC VDD NC A9 A7 A3 VDD BA0 S0 VSS DQ33 DQS4 VSS DQ40 DQ41 VSS DQ43 VDD VSS DQ49 DQS6 VSS DQ56 DQ57 VSS DQ59 SDA VDDSPD -
Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181 Pin 185 Pin 189 Pin 193 Pin 197
DQ17 - Pin 043 DQS2 - Pin 047 VSS - Pin 051 DQ33 - Pin 055 DQ25 - Pin 059 VSS - Pin 063 DQ27 - Pin 067 CB0/NC - Pin 071 VSS - Pin 075 CB2/NC - Pin 079 CB3/NC - Pin 083 VSS - Pin 087 CK2/NC - Pin 091 CKE1/NC - Pin 095 A12/NC - Pin 099 VSS - Pin 103 A5 - Pin 107 A1 - Pin 111 A10/AP - Pin 115 WE - Pin 119 A13/NC - Pin 123 DQ32 - Pin 127 VDD - Pin 131 DQ34 - Pin 135 DQ35 - Pin 139 VDD - Pin 143 DQS5 - Pin 147 DQ42 - Pin 151 VDD - Pin 155 VSS - Pin 159 DQ48 - Pin 163 VDD - Pin 167 DQ50 - Pin 171 DQ51 - Pin 175 VDD - Pin 179 DQS7 - Pin 183 DQ58 - Pin 187 VDD - Pin 191 SCL - Pin 195 VDDID - Pin 199
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 Pin 188 Pin 192 Pin 196 Pin 200 -
FRONTSIDE
BACKSIDE
DQ21 DM2 VSS DQ28 DQ29 VSS DQ31 CB4/NC VSS CB6/NC CB7/NC VSS VDD CKE0 A11 VSS A4 A0 BA1 CAS NC DQ36 VDD DQ38 DQ39 VDD DM5 DQ46 VDD CK1 DQ52 VDD DQ54 DQ55 VDD DM7 DQ62 VDD SA1 NC
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 Pin 186 Pin 190 Pin 194 Pin 198 -
Figure 1 Table 6 Density 512MB
Pin Configuration Diagram 200-Pin SO-DIMM Address Format Organization 64M x64 Memory Ranks 2 SDRAMs 32M x16 # of SDRAMs 8 # of row/bank/ columns bits 13/2/10 Refresh 8K Period 64 ms Interval 7.8 s
Data Sheet
12
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Pin Configuration
%$ %$ $ $Q 5$6 &$6 :( &.( &.( &. &. &. &.
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' &.( 6'5$0V ' ' ORDGV ORDGV
9''63' 9''9''4 95() 966 9'','
9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' ' 6WUDS VHH 1RWH 6&/ 6$' 6$ 6$ 6$ 966 6&/ 6$' $ $ $ :3 (
6 6 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6 ' /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' &6 ' '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '0 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '4 '4 '4 '4 '4 '4 '4 '4
/'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6
'
/'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '
&6
'
&6 /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6 /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6 /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6 /'0 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
03%'
Figure 2 Note:
Block Diagram Raw Card A x64 2 Ranks x16
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5%
Data Sheet
13
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 7 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT -0.5 VIN VDD VDDQ TA TSTG PD IOUT
-1 -1 -1 0 -55 - -
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 8 Parameter Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.5 2.3 2.5 2.3 0 0.49 x 0.5 x Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x V V V V V V V Unit Note/Test Condition 1)
VDD VDD Device Supply Voltage Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF
I/O Termination Voltage (System)
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4)
VTT
VDDQ VDDQ VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VDDQ VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6 V
1.4 --
5)
Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
14
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics Table 8 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ 8) -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 8) VOUT = 0.35 V 8)
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
15
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2
>
Current Specification and Conditions
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Symbol
IDD0
IDD1 IDD2P IDD2N
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
16
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 9
IDD Specification for HYS64D64020[H/G]DL-[5/6]-B
HYS64D64020GDL-5-B HYS64D64020HDL-5-B HYS64D64020GDL-6-B HYS64D64020HDL-6-B Unit Note 1)2)
Product Type
Organization
512MB x64 2 Ranks -5
512MB x64 2 Ranks -6 Max. 680 760 40 288 208 128 400 780 800 1360 13.6 1660 Typ. 510 570 20 200 140 90 300 570 590 1010 13.6 1250 Max. 620 680 30 240 192 120 352 676 696 1196 13.6 1480 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
Typ. 570 630 20 240 150 100 340 650 670 1130 13.6 1410
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
17
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
3.3
Table 10 Parameter
AC Characteristics
AC Timing - Absolute Specifications -6/-5 Symbol Min. -6 DDR333 Max. +0.7 +0.6 0.55 0.55 12 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.45 +0.55 -- -- -- -- -- -- 0.60 -- Min. -0.6 -0.5 0.45 0.45 5 6 7.5 0.4 0.4 2.2 1.75 -0.6 -0.6 0.75 -- -- -5 DDR400B Max. +0.6 +0.5 0.55 0.55 12 12 12 -- -- -- -- +0.6 +0.6 1.25 +0.40 +0.50 -- -- -- -- -- -- 0.60 -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit
Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.7 -0.6 0.45 0.45 6 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK
tDH tDS tIPW tDIPW tHZ
0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- --
2)3)4)5)6)
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time
2)3)4)5)7)
tDQSS tDQSQ tQHS tQH
tCK
ns ns ns
2)3)4)5)
TSOPII
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5)
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
DQS input low (high) pulse width (write tDQSL,H cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Write preamble setup time Write postamble Write preamble
tCK tCK tCK tCK
ns
2)3)4)5)
tDSS tDSH
2)3)4)5)
2)3)4)5)
Mode register set command cycle time tMRD
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPRES tWPST tWPRE
tCK tCK
Data Sheet
18
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics Table 10 Parameter AC Timing - Absolute Specifications -6/-5 (cont'd) Symbol Min. Address and control input setup time -6 DDR333 Max. -- -- Min. 0.6 0.7 -5 DDR400B Max. -- -- ns ns fast slew rate
3)4)5)6)10)
Unit
Note/ Test Condition 1)
tIS
0.75 0.8
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75 0.8
-- --
0.6 0.7
-- --
ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC
Read preamble period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay
0.9 0.40 42 60 72 18 18 18 12 15
1.1 0.60 70E+3 -- -- -- -- -- -- --
0.9 0.40 40 55 65 15 15 15 10 15
1.1 0.60 70E+3 -- -- -- -- -- -- --
tCK tCK
ns ns ns ns ns ns ns ns
tRFC tRCD tRP tRAP tRRD tWR tDAL
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)11)
tCK
1 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tWTR Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI
tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
19
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
SPD Contents
4
Table 11
SPD Contents
SPD Codes for HYS64D64020[H/G]DL-5-B HYS64D64020GDL-5-B 512 MB x64 2 Ranks (x16) HYS64D64020HDL-5-B 512 MB x64 2 Ranks (x16) PC3200S-3033-1 Rev 1.0 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 10 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 40 60 60 Rev. 1.0, 2004-05
Product Type Organization
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC3200S-3033-1 Rev 1.0 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 10 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 3C 28 40 60 60 21
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns]
Data Sheet
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 11 SPD Codes for HYS64D64020[H/G]DL-5-B HYS64D64020GDL-5-B 512 MB x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description PC3200S-3033-1 Rev 1.0 HEX 40 40 00 37 41 28 28 50 00 01 00 10 17 C1 00 xx 36 34 44 36 34 30 32 30 47 44 4C 35 42 20 20 20 20 20 0x 22 HYS64D64020HDL-5-B 512 MB x64 2 Ranks (x16) PC3200S-3033-1 Rev 1.0 HEX 40 40 00 37 41 28 28 50 00 01 00 10 17 C1 00 xx 36 34 44 36 34 30 32 30 48 44 4C 35 42 20 20 20 20 20 0x Rev. 1.0, 2004-05
Product Type Organization
tDS [ns] tDH [ns]
not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
Data Sheet
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 11 SPD Codes for HYS64D64020[H/G]DL-5-B HYS64D64020GDL-5-B 512 MB x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 99 -127 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) not used PC3200S-3033-1 Rev 1.0 HEX xx xx xx xx 00 HYS64D64020HDL-5-B 512 MB x64 2 Ranks (x16) PC3200S-3033-1 Rev 1.0 HEX xx xx xx xx 00
Product Type Organization
Table 12
SPD Codes for HYS64D64020[H/G]DL-6-B HYS64D64020GDL-6-B 512 MB x64 2 Ranks (x16) HYS64D64020HDL-6-B 512 MB x64 2 Ranks (x16) PC2700S-2533-0 Rev 0.0 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 Rev. 1.0, 2004-05
Product Type Organization
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC2700S-2533-0 Rev 0.0 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 23
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency
Data Sheet
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 12 SPD Codes for HYS64D64020[H/G]DL-6-B HYS64D64020GDL-6-B 512 MB x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 Description Write Latency DIMM Attributes Component Attributes PC2700S-2533-0 Rev 0.0 HEX 02 20 C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 00 00 00 00 3C 48 30 2D 55 00 00 00 00 0A C1 00 xx 36 24 HYS64D64020HDL-6-B 512 MB x64 2 Ranks (x16) PC2700S-2533-0 Rev 0.0 HEX 02 20 C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 00 00 00 00 3C 48 30 2D 55 00 00 00 00 0A C1 00 xx 36 Rev. 1.0, 2004-05
Product Type Organization
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
not used not used not used not used not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1
Data Sheet
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 12 SPD Codes for HYS64D64020[H/G]DL-6-B HYS64D64020GDL-6-B 512 MB x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 99 - 127 Description Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) not used PC2700S-2533-0 Rev 0.0 HEX 34 44 36 34 30 32 30 47 44 4C 36 42 20 20 20 20 20 0x xx xx xx xx 00 HYS64D64020HDL-6-B 512 MB x64 2 Ranks (x16) PC2700S-2533-0 Rev 0.0 HEX 34 44 36 34 30 32 30 48 44 4C 36 42 20 20 20 20 20 0x xx xx xx xx 00
Product Type Organization
Data Sheet
25
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL-[5/6]-B Small Outline DDR SDRAM Modules
Package Outlines
5
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
(2.15)
4 0.1
1
18.45 0.1 1.8 0.1 (2.4)
(2.45)
100
31.75
10.1
0.15
11.4 0.1
47.4 0.1
(2.7) (2.45) 1.5 0.1 10.1 101 200 (2.15)
4 0.1
6 0.1 20 0.1
2 MIN. Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1
Burnished, no burr allowed
L-DIM-200-006
Figure 3
Package Outlines - Raw Card A DDR-SDRAM SO-DIMM HYS64D64020[H/G]DL-[5/6]-B
Data Sheet
2.55
26
Rev. 1.0, 2004-05
www.infineon.com
Published by Infineon Technologies AG

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